A code template generator for VHDL. More...
#include <VHDLCodeTemplateGenerator.h>
Public Types | |
| typedef std::map< std::string, std::string > | port_map_type |
Public Member Functions | |
| VHDLCodeTemplateGenerator (std::string const &entity_name, std::string const &description, std::string const &logic_class) | |
| virtual | ~VHDLCodeTemplateGenerator () |
| virtual std::string | generate () const |
Protected Member Functions | |
| virtual std::string | generate_header () const |
| virtual std::string | generate_port_description () const |
| virtual std::string | generate_entity (std::string const &entity_name, std::string const &port_description="") const |
| virtual std::string | generate_component (std::string const &entity_name, std::string const &port_description) const |
| virtual std::string | generate_architecture (std::string const &entity_name, std::string const &header, std::string const &impl) const |
| virtual std::string | generate_impl (std::string const &logic_class) const |
| virtual std::string | generate_instance (std::string const &instance_name, std::string const &instance_type, port_map_type const &port_map) const |
| virtual std::string | generate_identifier (std::string const &name, std::string const &prefix="") const |
| Generate a VHDL complient identifier from a string. | |
Detailed Description
A code template generator for VHDL.
Definition at line 38 of file VHDLCodeTemplateGenerator.h.
Member Typedef Documentation
| typedef std::map<std::string, std::string> degate::VHDLCodeTemplateGenerator::port_map_type |
Definition at line 49 of file VHDLCodeTemplateGenerator.h.
Constructor & Destructor Documentation
| VHDLCodeTemplateGenerator::VHDLCodeTemplateGenerator | ( | std::string const & | entity_name, |
| std::string const & | description, | ||
| std::string const & | logic_class | ||
| ) |
Definition at line 31 of file VHDLCodeTemplateGenerator.cc.
| VHDLCodeTemplateGenerator::~VHDLCodeTemplateGenerator | ( | ) | [virtual] |
Definition at line 38 of file VHDLCodeTemplateGenerator.cc.
{
}
Member Function Documentation
| std::string VHDLCodeTemplateGenerator::generate | ( | ) | const [virtual] |
Implements degate::CodeTemplateGenerator.
Reimplemented in degate::VHDLTBCodeTemplateGenerator.
Definition at line 41 of file VHDLCodeTemplateGenerator.cc.
References degate::CodeTemplateGenerator::entity_name, generate_architecture(), generate_entity(), generate_header(), generate_impl(), generate_port_description(), and degate::CodeTemplateGenerator::logic_class.
{
return
generate_header() +
generate_entity(entity_name, generate_port_description()) +
generate_architecture(entity_name, "", generate_impl(logic_class));
}
| std::string VHDLCodeTemplateGenerator::generate_architecture | ( | std::string const & | entity_name, |
| std::string const & | header, | ||
| std::string const & | impl | ||
| ) | const [protected, virtual] |
Definition at line 182 of file VHDLCodeTemplateGenerator.cc.
References generate_identifier().
Referenced by degate::VHDLTBCodeTemplateGenerator::generate(), and generate().
{
boost::format f("architecture Behavioral of %1% is\n"
"%2%\n"
"begin\n"
"%3%\n"
"end Behavioral;\n\n");
f % generate_identifier(entity_name, "dg_")
% header
% impl;
return f.str();
}
| std::string VHDLCodeTemplateGenerator::generate_component | ( | std::string const & | entity_name, |
| std::string const & | port_description | ||
| ) | const [protected, virtual] |
Definition at line 81 of file VHDLCodeTemplateGenerator.cc.
References generate_identifier().
Referenced by degate::VHDLTBCodeTemplateGenerator::generate().
{
boost::format f(" component %1% is\n"
"%2%"
" end component;\n\n");
f % generate_identifier(entity_name, "dg_")
% port_description;
return f.str();
}
| std::string VHDLCodeTemplateGenerator::generate_entity | ( | std::string const & | entity_name, |
| std::string const & | port_description = "" |
||
| ) | const [protected, virtual] |
Definition at line 69 of file VHDLCodeTemplateGenerator.cc.
References generate_identifier().
Referenced by degate::VHDLTBCodeTemplateGenerator::generate(), and generate().
{
boost::format f("entity %1% is\n"
"%2%"
"end %3%;\n\n");
f % generate_identifier(entity_name, "dg_")
% port_description
% generate_identifier(entity_name, "dg_");
return f.str();
}
| std::string VHDLCodeTemplateGenerator::generate_header | ( | ) | const [protected, virtual] |
Reimplemented in degate::VHDLTBCodeTemplateGenerator.
Definition at line 48 of file VHDLCodeTemplateGenerator.cc.
References degate::CodeTemplateGenerator::entity_name.
Referenced by generate().
{
boost::format f("--\n"
"-- This is a VHDL implementation for a gate of type %1%\n"
"--\n"
"-- Please customize this code template according to your needs.\n\n"
"library ieee;\n"
"use ieee.std_logic_1164.all;\n\n");
f % entity_name;
return f.str();
}
| std::string VHDLCodeTemplateGenerator::generate_identifier | ( | std::string const & | name, |
| std::string const & | prefix = "" |
||
| ) | const [protected, virtual] |
Generate a VHDL complient identifier from a string.
VHDL identifier:
- Must begin with alphabetic characters (a-z or A-Z)
- Can contain alphanumeric (a-z, A-Z, 0-9) or underscore (_) characters
- Can be up to 1024 characters long
- Cannot contain white space
- are not case sensitive.
Implements degate::CodeTemplateGenerator.
Definition at line 197 of file VHDLCodeTemplateGenerator.cc.
Referenced by generate_architecture(), generate_component(), generate_entity(), generate_impl(), generate_instance(), and generate_port_description().
{
std::string identifier = prefix;
bool first_char = true;
BOOST_FOREACH(char c, name) {
if(c == '/' || c == '!') identifier.append("not");
else if(first_char && !isalpha(c)) {
//identifier.append("entity_");
identifier.push_back(c);
}
else if(isalnum(c)) identifier.push_back(c);
else identifier.push_back('_');
first_char = false;
}
return identifier;
}
| std::string VHDLCodeTemplateGenerator::generate_impl | ( | std::string const & | logic_class | ) | const [protected, virtual] |
Reimplemented in degate::VHDLTBCodeTemplateGenerator.
Definition at line 92 of file VHDLCodeTemplateGenerator.cc.
References degate::CodeTemplateGenerator::CLOCK, generate_identifier(), degate::CodeTemplateGenerator::get_inports(), degate::CodeTemplateGenerator::get_outports(), degate::CodeTemplateGenerator::get_port_name_by_type(), degate::CodeTemplateGenerator::logic_class, and degate::CodeTemplateGenerator::RESET.
Referenced by generate().
{
std::vector<std::string> in = get_inports();
std::vector<std::string> out = get_outports();
std::string clock_name = get_port_name_by_type(CLOCK);
if(clock_name.empty()) clock_name = "clock";
std::string reset_name = get_port_name_by_type(RESET);
if(reset_name.empty()) reset_name = "reset";
if(logic_class == "inverter" &&
in.size() == 1 && out.size() == 1) {
boost::format f(" %1% <= not %2%;");
f % generate_identifier(out[0]) % generate_identifier(in[0]);
return f.str();
}
else if((logic_class == "xor" ||
logic_class == "or" ||
logic_class == "and" ||
logic_class == "nor" ||
logic_class == "nand" ||
logic_class == "xnor") &&
in.size() >= 2 && out.size() == 1) {
std::string inner_op, outer_op = "not";
if(logic_class == "nand") inner_op = "and";
else if(logic_class == "nor") inner_op = "or";
else if(logic_class == "xnor") inner_op = "xor";
else {
outer_op = "";
inner_op = logic_class;
}
boost::format f(" %1% <= %2%%3%%4%%5%;");
f % generate_identifier(out[0])
% outer_op
% (outer_op.empty() ? "" : "(")
% boost::algorithm::join(generate_identifier<std::vector<std::string> >(in),
std::string(" ") + inner_op + std::string(" "))
% (outer_op.empty() ? "" : ")");
return f.str();
}
else if(logic_class == "flipflop-async-rst") {
boost::format f(
" -- \n"
" -- Please implement behaviour.\n"
" -- \n"
" -- process(%1%, %2%)\n"
" -- begin\n"
" -- if %3% = '1' then -- or '0' if RESET is active low...\n"
" -- Q <= '0';\n"
" -- elsif rising_edge(%4%) then\n"
" -- if Enable = '1' then -- or '0' if Enable is active low...\n"
" -- Q <= D;\n"
" -- end if;\n"
" -- end if;\n"
" -- end process;\n");
f % clock_name % reset_name
% reset_name
% clock_name;
return f.str();
}
else if(logic_class == "flipflop-sync-rst") {
boost::format f(
" -- \n"
" -- Please implement behaviour.\n"
" -- \n"
" -- process(%1%)\n"
" -- begin\n"
" -- if rising_edge(%2%) then\n"
" -- if RESET = '1' then\n"
" -- Q <= '0';\n"
" -- elsif Enable = '1' then -- or '0' if Enable is active low...\n"
" -- Q <= D;\n"
" -- end if;\n"
" -- end if;\n"
" -- end process;\n");
f % clock_name % clock_name;
return f.str();
}
else {
return
" -- \n"
" -- Please implement behaviour.\n"
" -- \n";
}
}
| std::string VHDLCodeTemplateGenerator::generate_instance | ( | std::string const & | instance_name, |
| std::string const & | instance_type, | ||
| port_map_type const & | port_map | ||
| ) | const [protected, virtual] |
Definition at line 217 of file VHDLCodeTemplateGenerator.cc.
References generate_identifier().
Referenced by degate::VHDLTBCodeTemplateGenerator::generate().
{
std::list<std::string> port_map_str;
BOOST_FOREACH(port_map_type::value_type p, port_map) {
boost::format m(" %1% => %2%");
m % generate_identifier(p.first) % generate_identifier(p.second);
port_map_str.push_back(m.str());
}
boost::format f(" %1% : %2% port map (\n%3%\n );\n\n\n");
f % generate_identifier(instance_name)
% generate_identifier(instance_type, "dg_")
% boost::algorithm::join(port_map_str, ",\n");
return f.str();
}
| std::string VHDLCodeTemplateGenerator::generate_port_description | ( | ) | const [protected, virtual] |
Definition at line 59 of file VHDLCodeTemplateGenerator.cc.
References generate_identifier(), degate::CodeTemplateGenerator::get_inports(), and degate::CodeTemplateGenerator::get_outports().
Referenced by degate::VHDLTBCodeTemplateGenerator::generate(), and generate().
{
boost::format f(" port(%1% : in std_logic;\n"
" %2% : out std_logic);\n");
f % boost::algorithm::join(generate_identifier<std::vector<std::string> >(get_inports()), ", ")
% boost::algorithm::join(generate_identifier<std::vector<std::string> >(get_outports()), ", ");
return f.str();
}
The documentation for this class was generated from the following files:
