A code template generator for VHDL. More...
#include <VHDLTBCodeTemplateGenerator.h>
Public Member Functions | |
| VHDLTBCodeTemplateGenerator (std::string const &entity_name, std::string const &description, std::string const &logic_class) | |
| virtual | ~VHDLTBCodeTemplateGenerator () |
| virtual std::string | generate () const |
Protected Member Functions | |
| virtual std::string | generate_header () const |
| virtual std::string | generate_impl (std::string const &logic_class) const |
| std::string | generate_signals () const |
| std::string | generate_clock_process (std::string const &clock_signal_name) const |
Detailed Description
A code template generator for VHDL.
Definition at line 38 of file VHDLTBCodeTemplateGenerator.h.
Constructor & Destructor Documentation
| VHDLTBCodeTemplateGenerator::VHDLTBCodeTemplateGenerator | ( | std::string const & | entity_name, |
| std::string const & | description, | ||
| std::string const & | logic_class | ||
| ) |
Definition at line 31 of file VHDLTBCodeTemplateGenerator.cc.
| VHDLTBCodeTemplateGenerator::~VHDLTBCodeTemplateGenerator | ( | ) | [virtual] |
Definition at line 37 of file VHDLTBCodeTemplateGenerator.cc.
{
}
Member Function Documentation
| std::string VHDLTBCodeTemplateGenerator::generate | ( | ) | const [virtual] |
Reimplemented from degate::VHDLCodeTemplateGenerator.
Definition at line 40 of file VHDLTBCodeTemplateGenerator.cc.
References degate::CodeTemplateGenerator::CLOCK, degate::CodeTemplateGenerator::entity_name, degate::VHDLCodeTemplateGenerator::generate_architecture(), generate_clock_process(), degate::VHDLCodeTemplateGenerator::generate_component(), degate::VHDLCodeTemplateGenerator::generate_entity(), generate_header(), generate_impl(), degate::VHDLCodeTemplateGenerator::generate_instance(), degate::VHDLCodeTemplateGenerator::generate_port_description(), generate_signals(), degate::CodeTemplateGenerator::get_inports(), degate::CodeTemplateGenerator::get_outports(), degate::CodeTemplateGenerator::get_port_name_by_type(), and degate::CodeTemplateGenerator::logic_class.
{
std::string tb_entity_name("testbench_");
tb_entity_name += entity_name;
port_map_type port_map;
BOOST_FOREACH(std::string const& port_name, get_inports()) port_map[port_name] = port_name;
BOOST_FOREACH(std::string const& port_name, get_outports()) port_map[port_name] = port_name;
std::string clock_process_impl;
std::string clock_signal_name = get_port_name_by_type(CLOCK);
std::cout << "clock signal is : " << clock_signal_name << std::endl;
if(!clock_signal_name.empty()) clock_process_impl += generate_clock_process(clock_signal_name);
return
generate_header() +
generate_entity(tb_entity_name) +
generate_architecture(tb_entity_name,
generate_component(entity_name,
generate_port_description()) +
generate_signals(),
generate_instance("uut", entity_name, port_map) +
clock_process_impl +
generate_impl(logic_class));
}
| std::string VHDLTBCodeTemplateGenerator::generate_clock_process | ( | std::string const & | clock_signal_name | ) | const [protected] |
Definition at line 107 of file VHDLTBCodeTemplateGenerator.cc.
Referenced by generate().
{
boost::format f(" constant clock_duration : time := 10 ns;\n\n"
" clk_proc : PROCESS (%1%)\n"
" BEGIN\n"
" IF rising_edge(%2%) then\n"
" %3% <= '0' AFTER clock_duration;\n"
" ELSE\n"
" %4% <= '1' AFTER clock_duration;\n"
" END IF;\n"
" END PROCESS clk_proc;\n\n\n");
f % clock_signal_name
% clock_signal_name
% clock_signal_name
% clock_signal_name;
return f.str();
}
| std::string VHDLTBCodeTemplateGenerator::generate_header | ( | ) | const [protected, virtual] |
Reimplemented from degate::VHDLCodeTemplateGenerator.
Definition at line 69 of file VHDLTBCodeTemplateGenerator.cc.
References degate::CodeTemplateGenerator::entity_name.
Referenced by generate().
{
boost::format f("--\n"
"-- This is VHDL testbench for a gate of type %1%\n"
"--\n"
"-- Please customize this code template according to your needs.\n\n"
"library ieee;\n"
"use ieee.std_logic_1164.all;\n\n");
f % entity_name;
return f.str();
}
| std::string VHDLTBCodeTemplateGenerator::generate_impl | ( | std::string const & | logic_class | ) | const [protected, virtual] |
Reimplemented from degate::VHDLCodeTemplateGenerator.
Definition at line 80 of file VHDLTBCodeTemplateGenerator.cc.
Referenced by generate().
{
boost::format f(" tb_proc : PROCESS is \n"
" BEGIN\n\n"
" -- \n"
" -- Please implement test.\n"
" -- \n\n"
" -- signal_name_a << '0';\n"
" -- signal_name_b << '0';\n"
" -- wait for clock_duration; \n"
" -- assert (signal_name_y == '0') report \"Got unexpected output.\" severity note;\n\n"
" END PROCESS tb_proc;\n\n\n");
return f.str();
}
| std::string VHDLTBCodeTemplateGenerator::generate_signals | ( | ) | const [protected] |
Definition at line 98 of file VHDLTBCodeTemplateGenerator.cc.
References degate::CodeTemplateGenerator::generate_identifier(), degate::CodeTemplateGenerator::get_inports(), and degate::CodeTemplateGenerator::get_outports().
Referenced by generate().
{
boost::format f(" signal %1% : in std_logic;\n"
" signal %2% : out std_logic;\n");
f % boost::algorithm::join(CodeTemplateGenerator::generate_identifier<std::vector<std::string> >(get_inports()), ", ")
% boost::algorithm::join(CodeTemplateGenerator::generate_identifier<std::vector<std::string> >(get_outports()), ", ");
return f.str();
}
The documentation for this class was generated from the following files:
