Screenshots
|
Main screenThe main screen with some dialog windows showing the list of standard cells and properties of a flip-flop. (Version 0.1.0) |
|
Design Rule ChecksRun Design Rule Checks in order to identify problems in your netlist. Failed checks are listet in a dialog window. (Version 0.0.9) |
|
Description of standard cell behaviourDescribe a standard cell's behaviour with free text, VHDL and Verilog. You can add testbenches for your code, too. If you define a logic class for your cell, degate will generate VHDL code stubs, because the software already knows your cell ports. For more complex standard cells like flipflops, degate generates code stubs where the architecture part is commented out. Degate recognises common ports like reset or clock, but not all port types. (Version 0.0.7) |
|
AnnotationsAnnotations are like bookmarks. You can annotate regions of interests, e.g. to mark any lettering on the silicon or to remember that you have to recapture images again due to image distortions. (Version 0.0.7) |
|
Working with subprojectsYou can keep your overview and detailed imagary at one place by means of subprojects. Via double-clicking on the highlighted area you can open a subproject. (Version 0.0.7) |
|
Connection InspectorThe Connection Inspector helps you to understand interconnections on register transfer level. (Version 0.0.6) |
|
Define port colorsYou can define colors for gate ports. This is a global setting and effects all ports from all gates with the given name.
(Version 0.0.6) |
|
Define a gridYou can define regular and irregular grids.
(Version 0.0.6) |
|
Main screen(Version 0.0.5) |
|
List of gate types / edit gate(Version 0.0.5) |
|
View menu(Version 0.0.5) |
